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In conjunction with the second annual IEEE/ACM International Symposium on Code Generation and Optimization (CGO) Palo Alto, California, March 21, 2004, researchers from both academia and industry have been invited to share their latest research findings in the area of EPIC architectures and compiler technology. The Explicitly Parallel Instruction Computing (EPIC) style of architecture was developed to enable new levels of instruction-level parallelism not achieved with traditional architectures. By allowing the compiler to express program parallelism and other relevant information directly to the processor, EPIC architectures can overcome hardware complexity issues that limit performance in traditional microprocessors. The major challenge to realizing the full potential of EPIC architectures is developing strategic compiler technologies that effectively deploy explicitly defined hardware mechanisms and deliver performance for both commercial and scientific applications. This half-day workshop will focus on promising research concepts that enable the EPIC architecture model. Some of the topics that will get discussed are:
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