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Codina.j___PPT9L/ 00P;L?  O  _4{07Virtual Cluster Scheduling Through the Scheduling Graph 8 c Josep M. Codina Jess Snchez Antonio Gonzlez Intel Barcelona Research Center, Intel Labs - UPC Fb2(Sr 0        ~1Clustered Architectures   Semiconductor technology is continuously improving New technologies pack more logic in a single chip Exploit more ILP More functional units, registers, etc. Faster clock cycles Current/future challenges in processor design Delay in the transmission of signals Power consumption Clustering: divide the system in semi-independent units Each unit Cluster Fast interconnects intra-cluster Slow interconnects inter-clusters Common trend in commercial VLIW processors Equator s MAP1000, TI TMS320C6x, ADI TigerSharc, HP/ST s Lx, & 3<.78C+Z?3) .         C?@      MOverview of the Architecture  RClustered VLIW Processors  Performance relies on the Compiler Code generation: Instruction Scheduling Register Allocation Cluster Assignment Hide delay due to inter-cluster communications Phase-ordering problem Decisions made for one task constraint possible decisions on the others Single-Phase approach4>/H4+ " H  ?Phase-Ordering Alternatives  Previous Work First Assign then schedule Accurate information of the assignment when scheduling However, schedule is constrained for the assignment Instructions scheduled and assigned at the same time Partially alleviates the ordering constraints However, no information from one task when performing the other Our Approach Perform both tasks at the same time but decisions aimed at assignment are delayed Accurate scheduling information when performing final assignment First instructions scheduled Partial assignment is built with the consequences of the scheduling decisions If a scheduling decision is not appropriate for assignment can be discarded Then, final assignment is performedddkP5dnP dRdAPdNPLP$dk5n   RANL  $$$  7 Talk Outline  tProposed algorithm Overview Scheduling Graph Virtual Clusters Deduction Process Performance evaluation Conclusions 6>$>$  X >Proposal Overview  Superblock Scheduling Single entry multiple exits GOAL: Minimize Average Weighted Completion Time (AWCT) Cycles between the entry and each exit weighted by the exit probability Our scheme enumerates AWCTRdS<cP+(c  /PProposal Overview  Superblock Scheduling Single entry multiple exits GOAL: Minimize Average Weighted Completion Time (AWCT) Cycles between the entry and each exit weighted by the exit probability Our scheme enumerates AWCT Single-phase approach scheduling and cluster assignment Delaying the cluster assignment decisions More information of the scheduling when making assignment decisions Impact of scheduling over assignment discovered and managed Main ingredients Scheduling Graph Describes all possible schedules Virtual Clusters Enable delaying the cluster assignment by keeping partial assignment Deduction Process Discovers most of the consequences of any decisions madeldS<cP8d*<Dx<Pdm<!Pm<EPm<9P+(c8  *D<  !$$((E,,00944  !IIngredient 1: Scheduling Graph  hDescribes all possible schedules Contains all feasible combinations between inst pairs that may overlapR"nGF" $ i %KScheduling Based on SG  Choose some combinations while discard others Chosen combinations create complex instructions Schedule each complex instruction in a cycleD.P0-P.-  !Ingredient 2: Virtual Clusters  Virtual Cluster Set of instructions to be mapped into the same physical cluster Multiple virtual clusters can be mapped into the same physical cluster However, not all virtual clusters can be mapped into the same phsical cluster Not enough resources to accommodate both VCs in the same physical cluster VCG: Undirected Graph Each node is a virtual cluster When an edge (VC1,VC2) exists, VC1 and VC2 are incompatible VC1 and VC2 must be mapped into different physical clusters VCG managed by the deduction process Clusters are fused Clusters become incompatible Communications are added When a pair producer-consumer belong to incompatible clustersn@FnJZn[F<Z%nIF>Z/I    /       0%I  >$$&   HIngredient 3: Deduction Process  Every decision considered is submitted to the deduction process Discovers most of the consequences of any decisions Improves the knowledge to make appropriate decisions Anticipate invalid decisions Avoid non-valid schedules in advance Process based on rules Interaction between resources and dependences Cluster assignment A rule Takes a decision or a change on the state as a input Examines the current state Concludes mandatory changes to apply over the state@n4F5FZ%FnAFnF@45%  A  6TIngredient 3: Deduction Process  EEvery decision considered is submitted to the deduction process Discovers most of the consequences of any decisions Improves the knowledge to make appropriate decisions Anticipate invalid decisions Avoid non-valid schedules in advance Process based on rules Interaction between resources and dependences Cluster assignment A rule Takes a decision or a change on the state as a input Examines the current state Concludes mandatory changes to apply over the state Changes feed back to the process Consequences of consequences discovered Process finishes when no change to be treated@n4F5FZ%FnAFnF!nVF@45%  A!V F xAlgorithm Overview   &Algorithm Overview   4Algorithm Overview   )MAlgorithm Overview   3SAlgorithm Overview   7UAlgorithm Overview   ;Experimental Environment  CCARS Single-Phase approach List-schedule giving priority to instructions in the critical path of the DG Schedules and Assigns instructions at the same time For each instruction, the scheduling cycle for each cluster is computed the cluster that allows for the schedule of the instruction in the earliest cycle is selected instruction becomes assigned and scheduled in the selected cluster In contrast to our approach It does not study the consequences before making a decision It simply updates the estart of all successors as a consequence of a decision to the scheduling statex" dxxx   D 1QExperimental Environment  Impact compiler Profiling information on the superblock exit probabilities execution frequency of each superblock Configurations Three different ones 2-clusters 1 Interconnect Bus with 1 cycle latency 4-clusters 1 Interconnect Bus with 1 cycle latency 4-clusters 1 Interconnect Bus with 2 cycle latency Each cluster able to execute 1 Int, 1 FP, 1 Mem, 1 Branch Perfect Memory Non-constrained number of registers Benchmarks 7 SpecInt95 and 7 MediaBench(Ln((Ln  (ZP     \    Performance Results   Conclusions  Single-phase scheduling and cluster assignment Delaying the cluster assignment Key features Scheduling Graphs Virtual Clusters Deduction Process Our approach applied to superblocks performs better than CARS Avg speedup close 10% for 4 clusters 1 bus latency 2 Up to 14% for some programs Improvements come from More information of the effects of all decisions made Reducing the probabilities to made erroneous decisions Allowing for a better interaction between scheduling and assignment$/d < d5<>dQnd6<7PD</  5>f&f  67D&   D7Virtual Cluster Scheduling Through the Scheduling Graph 8 c Josep M. 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V    @` @= Zvf)?" cI !   @`B A= To ?"B B= N1 ?"B C= To ?"B D= To ?"B E= To ?"? HnQ F=# #" ,$@0 G= Z= )?"Hn V    @` H= Z = )?"HnQ V    @` I= Zı= )?"Hn cB !   @`B J= To ?"HnB K= N1 ?"HnB L= To ?"HQnQB M= To ?"HHQB N= To ?"nnQB O= H1 ?"Hn  P=# #"i>,$@0 Q= Z = f)?" V    @` R= Z8= f)?" cI !   @`B S= To ?"B T= N1 ?"B U= To ?"B V= To ?"B W= To ?"? $ X=# #" 8,$@0 Y= ZH= )?"U V    @` Z= Z@= )?"U$ V    @` [= ZX= )?" cB !   @`B \= To ?"B ]= N1 ?"B ^= To ?"$$B _= To ?"$B `= To ?"$B a= H1 ?"UU   b b=# #"  ' ,$@0 c= Z= f)?"  b V    @` d= Z= f)?"   _I    @`B e= To ?"  B f= N1 ?"  B g= To ?" b bB h= To ?"  bB i= To ?"  b;  Q j=# #"  ,$@0 k= Z> )?"  V    @` l= Z> )?" Q V    @` m= Zp> )?"  _B    @`B n= To ?" B o= N1 ?" B p= To ?"Q QB q= To ?"QB r= To ?"  QB s= H1 ?"   t=# #" @ ,$@0 u= ZP!> f)?" V    @` v= Zh*> f)?" cI !   @`B w= To ?"B x= N1 ?"B y= To ?"B z= To ?"B {= To ?"?  FR |=# #"  ,$D 0 }= Zx5> )?" F V    @` ~= Zp>> )?" FR V    @` = ZG> )?" F cB !   @`B = To ?" FB = N1 ?" FB = To ?" RFRB = To ?"  RB = To ?"FFRB = H1 ?" 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