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O =?*{0/Heterogeneous Clustered VLIW Microarchitectures 0 ? Alex Alet, Josep M. Codina, Antonio Gonzlez and David Kaeli R(>2 2 @ Clustered Microarchitectures  Challenges in processor design Wire delays Power consumption Clustering: divide the system into semi-independent units Each unit Cluster Fast interconnects intra-cluster Slow interconnects inter-clusters Common trend in commercial VLIW processors DSP/embedded domain:C+ .  C+    Clustered VLIW Architecture  & Motivation  ;Not all instructions have the same impact on execution time < R Motivation  V Motivation   Talk Outline  eHeterogeneous Clustered Architecture Proposed Compiler Techniques Experimental Evaluation Conclusions f 0Heterogeneous Architecture  ?Configured similar to a multiple clock domain design Domain boundaries: Each cluster Inter-connection Network Memory hierarchy Each domain can use a different voltage / frequency Performance oriented: higher voltage/frequency Power oriented: lower voltage/frequency Communication between domains: synchronization queuesv574W6574  W  6   @  Heterogeneous Architecture  Distributed Control Path  XFetch and decode units distributed among clusters Instruction lay-out Grouped by cluster:22 Y X Talk Outline  eHeterogeneous Clustered Architecture Proposed Compiler Techniques Experimental Evaluation Conclusions*f%$ f Statically Scheduled Processors  Performance relies on the compiler Instruction scheduling Register allocation Clustered microarchitectures Cluster assignment Communications Multimedia and numeric code Majority of the execution in loop bodies Modulo schedulingv#H";#H"  ;  Modulo Scheduling  WEffective technique for scheduling loops Overlaps loop iterations Increases parallelism*)d/d)/ X *MS for Heterogeneous   \Proposed Technique   d^Select Voltages and Frequencies  For each domain At program level Consider different delays between fast and slow domains Estimate execution time Estimate energy consumption Select minimum ED2<YGYE  .Estimate Execution Time  Use profiling Texec= niters (II + SC - 1) Tcycle Estimated IT Enough to accommodate All instructions All recurrences Value lifetimes of the profiled homogeneous Communications required by the profiled homogeneous ' !`}   !  `     E            6 NEstimate Energy Consumption  ZSame microarchitecture, different voltages Relative dynamic power Relative static power&+0+0 [ 6 MS Algorithm   J MS Algorithm   ,MS for Heterogeneous  Multilevel graph partitioning algorithm Coarsening Place critical recurrences in fast clusters Refinement Estimate execution time and energy consumption Optimize for ED2 Scheduling Instructions delayed due to synchronization hazards( , @ 4( , >      4  >Recurrence Constrained Loops  VLarge benefits expected A small number of instructions are critical for execution time&?? W Z Talk Outline  eHeterogeneous Clustered Architecture Proposed Compiler Techniques Experimental Evaluation Conclusions*fB  f DExperimental Environment  AMicroarchitecture Clusters 4 clusters 1 FP-unit, 1 INT-unit, 1 memory port, 16 registers per cluster Inter-connection Network 1-cycle latency broadcast buses Heterogeneity Clusters: 1 performance oriented / 3 power oriented Benchmarks: SpecFP2k Fortran programs Loops obtained with ORC Baseline: homogeneous architecture K 4 2# K   4 2# B HResults  BHigh ILP Programs  All instructions have a similar impact on execution time No benefit using different frequencies Higher IPC Dynamic energy accounts for a majority of the total energy consumption Use lower Vdd and lower frequencies Memory hierarchy and inter-connection network can use different voltagesf92kI92RI&  ` _ Talk Outline  eHeterogeneous Clustered Architecture Proposed Compiler Techniques Experimental Evaluation ConclusionsfZ  f ? Conclusions  |Heterogeneous clustered architectures Clusters run at different voltages / frequencies Instructions that impact execution time scheduled in fast clusters Remaining instructions in power-oriented clusters Proposed compiler techniques Algorithm to select the voltages / frequencies MS for heterogeneous configurations ED2 : 15% improvement on average Up to 35% for selected programs&1uS! &1u  S    } /Heterogeneous Clustered VLIW Microarchitectures 0 ? Alex Alet, Josep M. Codina, Antonio Gonzlez and David Kaeli R(>2 2 @ xMotivating Example  Heterogeneous Architecture  Signals  Branch Instructions  Branches decoupled in several instructions (Unbundled Branch Architecture) Branch target computation Independent in each cluster Branch condition evaluation Computed in one cluster Broadcasted to the rest Control transfer Different in each cluster K0K0        ;Results  ]Recurrence Constrained Loops  Largest benefits obtained A small number of instructions are critical for execution time Improvement: 30% - 35% for 189.lucas and 200.sixtrack&uu  Smallest Benefits  ~Around 5% 168.wupwise Loops have different characteristics 173.applu Low number of iterations Schedule length has a big impactb % : % :    /Zbo#'+-/17<@ACEIKOSWY[^`: 0` ̙33` 3` 3333f` 999MMM` f` f3` 3>?" dd@ ?qdx@umKP 5xd@ " `-d3 n?" dd@   @@``PZn   @ ` ` p>>   >6 (  :  Tgֳgֳ ?`  RClick to edit Master text styles Second level Third level Fourth level Fifth level!     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Bo ?"0@NNN?N(B / <1 ?"0@NNN?N(B 0 Bo ?"0@NNN?N  (B 5 <1 ?"0@NNN?N(B : <1 ?"0@NNN?N  (B ? <1 ?"0@NNN?N00( f HtE f?"6@ NNN?Nl g Homogeneous (2 33 B g TDԔ?"0@NNN?N 0,$D0B h TDԔ?"0@NNN?N 0,$@0b j NG+IPF?"6@`NNN?N@ ,$D0\ k T E f??"6@`NNN?N0 i@P ,$0 f Scheduling (2 33 H  0޽h ?           !" !# ̙33~___PPT10^+D '  = @B D' = @BA?%,( < +O%,( < +D' =%(D' =%(DG' =4@BBB B%(D' =1:Bvisible*o3>+B#style.visibility<*j%(D' =-6B'blinds(horizontal)*<3<*jD' =%(D' =A@BBBB0B%(D' =1:Bvisible*o3>+B#style.visibility<*k%(D' =%(D' =4@BBBB%(D' =1:Bvisible*o3>+B#style.visibility<*%(D' =%(D' =4@BBBB%(D' =1:Bhidden*o3>+B#style.visibility<*j%(DF' =%(D' =%(DG' =4@BBB B%(D' =1:Bvisible*o3>+B#style.visibility<*h%(D' =-6B'blinds(horizontal)*<3<*hDG' =4@BBB B%(D' =1:Bvisible*o3>+B#style.visibility<*g%(D' =-6B'blinds(horizontal)*<3<*g+8+0+k0 + 0 rrxp(    T3f3f|?"6@`NNN?Ns   T3f3f|?"6@`NNN?N"   T|?"6@`NNN?Nz~  s *YD `  E  = =  #"6* =<$D0 D .   `/ ##f?"6@ NNN?N =  X  @`.   `/E ##f?"6@ NNN?N   X  @`.    `h1E ##f?"6@ NNN?N  X  @`7    `1E ##f?"6@ NNN?N/  aA  @`/   ZDRE ##f?"6@ NNN?N/  _0  @`.    `P[E ##f?"6@ NNN?N = X  @`7    `cE ##f?"6@ NNN?N   aN  @`7   `4mE ##f?"6@ NNN?N  aK  @`7   `vE ##f?"6@ NNN?N/ aG  @`/  ZE ##f?"6@ NNN?N/ _6  @`.   `dqE ##f?"6@ NNN?N A = X  @`7   `(E ##f?"6@ NNN?N/A  aF  @`/  ZE ##f?"6@ NNN?NA / _5  @`.   `E ##f?"6@ NNN?N f =A  X  @`7   ``E ##f?"6@ NNN?N f  aM  @`7   `E ##f?"6@ NNN?Nf  aJ  @`7   `оE ##f?"6@ NNN?N/f A  aE  @`/  ZE ##f?"6@ NNN?Nf /A  _4  @`.   `E ##f?"6@ NNN?N =  X  @`7   `E ##f?"6@ NNN?N f  aL  @`7   `E ##f?"6@ NNN?N f  aI  @`7   `E ##f?"6@ NNN?N/   aC  @`/  ZE ##f?"6@ NNN?N /  _2  @`.    `lE ##f?"6@ NNN?N =f  X  @`7 #  `G ##f?"6@ NNN?N/ f  aD  @`/ $ ZG ##f?"6@ NNN?N /f  _3  @`. &  `G ##f?"6@ NNN?N = X  @`7 (  `"G ##f?"6@ NNN?N/ aH  @`/ ) Z(+G ##f?"6@ NNN?N/ _7  @`; *  `@4G ##f?"6@ NNN?N =  eCom A  @`7 +  `D=G ##f?"6@ NNN?N/   aB  @`/ , ZL?G ##f?"6@ NNN?N /  _1  @`% / N Bo?"0@NNN?N B ? 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( e# #"HHl0 G 8 f NԽG f?"6@ NNN?N0( t Cycle time   @` g TG ?"6@ NNN?N0 T  @`+ h TG f?"6@ NNN?N ( a2  @`( i TlG ?"6@ NNN?N  ^C2  @`+ j TG f?"6@ NNN?N( a2  @`( k TG ?"6@ NNN?N ^C1  @`+ l TG f?"6@ NNN?N  ( a1  @`+ m T$G f?"6@ NNN?N0( a1  @`) n TH ?"6@ NNN?N   _ICN  @`( o TH ?"6@ NNN?N0 ^C0  @`B p Bo ?"0@NNN?N B q <1 ?"0@NNN?N B r Bo ?"0@NNN?N( (B s Bo ?"0@NNN?N(B t <1 ?"0@NNN?N(B u Bo ?"0@NNN?N  (B v <1 ?"0@NNN?N(B w <1 ?"0@NNN?N  (B x <1 ?"0@NNN?N00( y HH f?"6@ NNN?Nl i Heterogeneous(233 2  NfԔ?"6@`NNN?Np x,$D0b  NG+IPF?"6@`NNN?N@ ,$D0\  T H f??"6@`NNN?N0 i@P ,$0 f Scheduling (2 33 H  0޽h ?VWYWXZ[\^\]_X[`]abHIKIJL VHM VQN QRS RPT acd ̙337 / ___PPT10 +1`D '  = @B Dv ' = @BA?%,( < +O%,( < +D' =%(D' =%(DG' =4@BBB B%(D' =1:Bvisible*o3>+B#style.visibility<*%(D' =-6B'blinds(horizontal)*<3<*D' =%(D' =%(DG' =4@BBB B%(D' =1:Bvisible*o3>+B#style.visibility<*%(D' =-6B'blinds(horizontal)*<3<*D' =%(D' =A@BBBB0B%(D' =1:Bvisible*o3>+B#style.visibility<*%(D' =%(D' =4@BBBB%(D' =1:Bvisible*o3>+B#style.visibility<*%(D' =%(D' =4@BBBB%(D' =1:Bhidden*o3>+B#style.visibility<*%(+8+0+0 + o0 pd *(  d x d c $@޺ `   r d S ޺     H d 0޽h ? ̙33___PPT10+D'  = @B D]' = @BA?%,( < +O%,( < +D' =%(D<' =%(D' =4@BBBB%(D' =,54 *3>!Bstyle.color='`B@BPB<*d %BD' =4@BBBB%(D' =,54 *3>!Bstyle.color='`B@BPB<*d BZD' =4@BBBB%(D' =,54 *3>!Bstyle.color='`B@BPB<*d Zf+ 0 |6(  |~ | s *H `  H  x | c $X H   H  H | 0޽h ? ̙33y___PPT10Y+D='  = @B +BT 0 JJsD( I(  D^2 sD 6o ` 0 tD 6H 3f B p V DATA CACHE     d2 qD <o@ P dB uD <D)K KdB vD <D) h wD  @0e0e    BCDE|F6 1 8c8c     ?1 d0u0@Ty2 NP'p<'pA)BCD|E||r`[uysjX@@ sUI;n , KQ~ Zz:Fvzr@          ` j  xD  0e0e    BCMDEFN 1 8c8c     ?1 d0u0@Ty2 NP'p<'pA)BCD|E||11B/ ~3ywf#M D6+!!ZzB- "$,cyMB6,  /"?MMFz:+3/Q0n6z8BB$(@                `; @  yD  0e0e    BCDEFJ 1 8c8c     ?1 d0u0@Ty2 NP'p<'pA)BCD|E||..nJ$n !Gd/3,Ys *7=7+yM] 77\"$@               `'  F    D   ` {D 0f   |D 6uH 33&    OINT   lB }D <Dp O p  lB ~D <D O  lB D <D O  lB D <D O   D 6 {H 33   OINT   lB D <D O  lB D <D: O :  lB D <Dj O j  lB D <D: O :   D 6H 33    NFP   lB D <D@O @ lB D <DpO p lB D <DO  lB D <DpO p  D 6 H 33   NFP   lB D <DO  lB D <D O  lB D <D:O : lB D <D O   D 6H 33   OMEM   lB D <DO  lB D <D@O @ lB D <DpO p lB D <D@O @  D 6H 33` P  OMEM   lB D <DO  lB D <DO  lB D <D O  lB D <DO  f2 D 62 d G y f2 D 6\ d p y f2 D 6 d y f2 D 6d y f2 D 6/d Cy f2 D 6Xd my f2 D 6a v f2 D 6a v f2 D 6 a 5v  D 6dH  /PO  Y REGISTER FILE     D 3 rH _ж_ж?"P QI-CACHE  ^r D 6G{|2 D To? ` 6^ D 6oH )W ~ D s *PH `  H  R D s *P;  D 6H   ] CLUSTER 1$    jB D BD cc jB D BDdB D <D>dB  D <D>   D 6H f@  ] CLUSTER 2$    jB  D BD  jB  D BDjB  D BD D 6H fg  ] CLUSTER N$    jB D BD  jB D BDjB D BDjB D BD   D 6LH 3f ` W MAIN MEMORY     D BH  C TRegister buses   X2 D 0J f X2 D 0J f X2 D 0J <f  D 0H @` : dClustered VLIW processor   D NT`H 1?   \ DATA CACHE"    8 / D/T  h  D#   D N1?"6@`NNN?N  D N1?"6@`NNN?N h D N1?"6@`NNN?N  B D ZD|? "0@NNN?N89/B D ZD|? "0@NNN?N89 D T|?"6@`NNN?NL c   D#  I f2 D 6c w f2 D 6  f2 D 6  L  6  D#  6 N  h  D  68  D N1?"6@`NNN?N  D N1?"6@`NNN?N h D N1?"6@`NNN?N  B D TD|?"0@NNN?N  B D TD|?"0@NNN?N0   D ZH jJ?"6@`NNN?N8p,$@ 0 synchronization queues4R D  `ZGH!I|?"0@NNN?N6 ,$D 0b D  `G)H#I|?"0@NNN?Nk,$@ 0jB D BDccL  6  D#   N  h  D  68  D N1?"6@`NNN?N  D N1?"6@`NNN?N h D N1?"6@`NNN?N  B D TD|?"0@NNN?N  B D TD|?"0@NNN?N0  B D ZD|? "0@NNN?NG@@F / D  /T  h  D#  D N1?"6@`NNN?N  D N1?"6@`NNN?N h D N1?"6@`NNN?N  B D TD|?"0@NNN?N89/H D 0޽h ??`qDsDDDDDDDD ̙33___PPT10+8s^Dz'  = @B D5' = @BA?%,( < +O%,( < +Dl' =%(D' =%(D9' =4@BBBB%(D' =1:Bvisible*o3>+B#style.visibility<*D%(D' =-u6Bwipe(right)*<3<*DD@' =A@BBBB0B%(D' =1:Bvisible*o3>+B#style.visibility<*D%(D' =-o6Bwipe(up)*<3<*DD3' =4@BBBB%(D' =1:Bvisible*o3>+B#style.visibility<*D%(D' =-o6Bwipe(up)*<3<*D+8+0+D0 +C 0 bJZJ@G@I(  ~  s *H `  H  x  c $tH 0  H  l    ? Xh ` ,$D 0\ < 3 rH жж?"6@`NNN?N  tI1C1@       \ = 3 r$H жж?"6@`NNN?NJ   tI3C1@       \ > 3 rlH жж?"6@`NNN?N J  tI2C1@       z    @  0` ,$@0\ A 3 r4H жж?"6@`NNN?N  tI1C2@       \ B 3 rdH жж?"6@`NNN?NJ   tI3C2@       \ C 3 r(H жж?"6@`NNN?N J  tI2C2@       z    D `  ,$@0\ E 3 rQ жжd?"6@`NNN?N  tI1C3@       \ F 3 rQ жжd?"6@`NNN?NJ   tI3C3@       \ G 3 r Q жжd?"6@`NNN?N J  tI2C3@       z    H `  ,$@0\ I 3 rQ жж?"6@`NNN?N  tI1C4@       \ J 3 rQ жж?"6@`NNN?NJ   tI3C4@       \ K 3 r8Q жж?"6@`NNN?N J  tI2C4@       l R  Z| ` ,$D 0@  J  LP \ 8 3 r$Q жж?"6@`NNN?N :  tI1C1@       \ 9 3 r@+Q жж?"6@`NNN?NJ  tI1C4@       \ : 3 r1Q жжd?"6@`NNN?N   tI1C3@       \ ; 3 r7Q жж?"6@`NNN?N:   tI1C2@       N  J  M @P \ N 3 rD=Q жж?"6@`NNN?N :  tI2C1@       \ O 3 r,DQ жж?"6@`NNN?NJ  tI2C4@       \ P 3 r@Q жжd?"6@`NNN?N   tI2C3@       \ Q 3 r PQ жж?"6@`NNN?N:   tI2C2@       N  J  R @P \ S 3 r|UQ жж?"6@`NNN?N :  tI3C1@       \ T 3 r[Q жж?"6@`NNN?NJ  tI3C4@       \ U 3 rXQ жжd?"6@`NNN?N   tI3C3@       \ V 3 rgQ жж?"6@`NNN?N:   tI3C2@        W # l_ж_жf|?"6@`NNN?NP  X # l_ж_жf|?"6@`NNN?N@R  Y # l_ж_жf|?"6@`NNN?N@R  [  `+B#style.visibility<*[%(D' =-6B'blinds(horizontal)*<3<*[D' =%(Dq' =4@BB BB%()))D' =1:Bvisible*o3>+B#style.visibility<*Z%(D' =-}6B!slide(fromLeft)*<3<*ZD' =%(D' =4@BBBB%(D' =1:Bvisible*o3>+B#style.visibility<*a%(Dr' =%(D' =%(D5' =4@BB?BB%()?)?D' =.Q7 BBBBBcM -3.61111E-6 -4.16185E-6 L 0.30191 -4.16185E-6 *3>*B ppt_xB ppt_y=@0BBAApBB(}>B<*aD' =%(D-' =4@BB?BB%()?)?D' =.I7 BBBBB[M 0.30191 -4.16185E-6 L 0.60191 -4.16185E-6 *3>*B ppt_xB ppt_y=@0BBAApBB>B<*aD@' =%(D' =%(DT' =A@BBB B0B%(D' =1:Bvisible*o3>+B#style.visibility<*m%(D' =-6B'blinds(horizontal)*<3<*mD' =A@BBBB0B%(D' =1:Bvisible*o3>+B#style.visibility<*%(D' =4@BBBB%(D' =1:Bhidden*o3>+B#style.visibility<*a%(D-' =%(D?' =4@BB BB%(,D' =1:Bvisible*o3>+B#style.visibility<*b%(D' =-{6Bslide(fromTop)*<3<*bDC' =4@BB BB%(D' =1:Bvisible*o3>+B#style.visibility<*c%(D' =-6B#slide(fromRight)*<3<*cDC' =4@BB BB%(D' =1:Bvisible*o3>+B#style.visibility<*d%(D' =-6B#slide(fromRight)*<3<*dD' =%(D' =4@BBBB%(D' =1:Bvisible*o3>+B#style.visibility<*?%(D' =%(D' =%(D' =4@BBBB%(D' =1:Bhidden*o3>+B#style.visibility<*d%(D' =4@BBBB%(D' =1:Bhidden*o3>+B#style.visibility<*c%(D' =4@BBBB%(D' =1:Bhidden*o3>+B#style.visibility<*b%(D%' =%(D?' =4@BB BB%(D' =1:Bvisible*o3>+B#style.visibility<*f%(D' =-{6Bslide(fromTop)*<3<*fD?' =4@BB BB%(D' =1:Bvisible*o3>+B#style.visibility<*g%(D' =-{6Bslide(fromTop)*<3<*gD?' =4@BB BB%(D' =1:Bvisible*o3>+B#style.visibility<*h%(D' =-{6Bslide(fromTop)*<3<*hDu' =%(D' =4@BBBB%(D' =1:Bvisible*o3>+B#style.visibility<*@%(D' =A@BBBB0B%(D' =1:Bvisible*o3>+B#style.visibility<*i%(D' =%(D' =%(D' =4@BBBB%(D' =1:Bhidden*o3>+B#style.visibility<*f%(D' =%(D' =4@BBBB%(D' =1:Bhidden*o3>+B#style.visibility<*g%(D' =%(D' =4@BBBB%(D' =1:Bhidden*o3>+B#style.visibility<*h%(D ' =%(D' =4@BBBB%(D' =1:Bvisible*o3>+B#style.visibility<*D%(D' =4@BBBB%(D' =1:Bvisible*o3>+B#style.visibility<*H%(D' =A@BBBB0B%(D' =1:Bvisible*o3>+B#style.visibility<*j%(D' =A@BBBB0B%(D' =1:Bvisible*o3>+B#style.visibility<*k%(D' =A@BBBB0B%(D' =1:Bvisible*o3>+B#style.visibility<*l%(D' =A@BBBB0B%(D' =1:Bvisible*o3>+B#style.visibility<*l%(D' =A@BBBB0B%(D' =1:Bvisible*o3>+B#style.visibility<*k%(D' =A@BBBB0B%(D' =1:Bvisible*o3>+B#style.visibility<*j%(D' =%(D' =4@BBBB%(D' =1:Bvisible*o3>+B#style.visibility<*s%(D' =%(D' =4@BBBB%(D' =1:Bvisible*o3>+B#style.visibility<*r%(D' =%(D' =4@BBBB%(D' =1:Bvisible*o3>+B#style.visibility<*%(D' =%(D' =4@BBBB%(D' =1:Bvisible*o3>+B#style.visibility<*%(+0+0+[0 ++0+i0 ++0+j0 ++0+j0 ++0+k0 ++0+k0 ++0+l0 ++0+l0 ++0+m0 ++0+0 + 0  6(  ~  s *,z} `  }  x  c $$}   }  H  0޽h ? ̙33y___PPT10Y+D='  = @B + 0  6(  ~  s *xQ `  Q  x  c $PQ X0` Q  H  0޽h ? ̙33y___PPT10Y+D='  = @B +u\ 0 JJ Y H(   2 e  `_ж_ж3 Ԕ?#" `  ! ,$@08 t1  t1   # lhP жж3 ?"t 1 ccycle 6   @`   # lxP жж3 ?"t   ccycle 5   @`   # lxP жж3 ?"t   ccycle 4   @`   # lP жж3 ?"t   ccycle 3   @`   # lؔP жж3 ?"tx  ccycle 2   @`   # lP жж3 ?"tx ccycle 1   @`   fP _ж_ж3 ?#" `   R   @`   fP _ж_ж3 ?#" `x  R   @`   ftP _ж_ж3 ?#" `x R   @`B !  f_ж_ж?"tB "  f_ж_ж?"1t1B #  f_ж_ж?"ttxB %  f_ж_ж?" xB &  f_ж_ж?"HB '  f_ж_ж?"HB (  f_ж_ж?" B *  f_ж_ж?"x  B ,  f_ж_ж?" B .  f_ж_ж?" tt B /  f_ж_ж?" tt B 0  f_ж_ж?" tt1B 4  f_ж_ж?"xtt B 6  f_ж_ж?" tt B 9  f_ж_ж?"11~ C s *P `  P  ~ D s *̽P X   P   F WJ > E  WJ >B F # l_ж_жD?":J : G   fP _ж_ж3 ?"W> WIteration space  l @ 1  H( 1,$D0l@ H    @      f`P _ж_ж3 ?#" `H   R   @`    fP _ж_ж3 ?#" `H   R   @`    f@P _ж_ж3 ?#" `H   R   @`l@  1   x 1    fP _ж_ж3 ?#" ` 1 R   @`    f8P _ж_ж3 ?#" `  R   @`    fP _ж_ж3 ?#" `   R   @`N 2p0  H  " N  '  I  2 @  2 J  3 rP _ж_ж31?#" ` '  KA   2 K  3 rP _ж_ж31?#" ` ''  KB   2 L  3 rW _ж_ж31?#" ` '  KC   M   f_ж_ж?"   N   f_ж_ж?"'  & O   fW _ж_ж3 ?"p0 D  z4th ItD   P B # l_ж_ж1?"D q N 2p2  Q  l N  '  R  2 @  2 S  3 rh W _ж_ж31?#" ` '  KA   2 T  3 rW _ж_ж31?#" ` ''  KB   2 U  3 rXW _ж_ж31?#" ` '  KC   V   f_ж_ж?"   W   f_ж_ж?"'  & X   fW _ж_ж3 ?"p2 D  z3rd ItD   Y B # l_ж_ж1?"D q L  '  Z # >Sa^  2 [  3 r W _ж_ж31?#" ` '  KA   2 \  3 r W _ж_ж31?#" ` ''  KB   2 ]  3 rp#W _ж_ж31?#" ` '  KC   ^   f_ж_ж?"   _   f_ж_ж?"'   `  `'W _ж_ж3 ?"a z1st ItD   a @  f_ж_ж1?"9f F p  b  YJB c  3 rZ_ж_жD?"p  d  # l-W _ж_ж3 ?"e   LTime  tz  0     0 ,$D0 m   f_ж_ж3 8c?#" ` 8 n  # l2W _ж_ж3 ?" 0  (Kernel: pattern repeated every II cycles.) )  8  0   0hN  1    E0    `9W _ж_ж3 ?#" ` 1 R   @`    `GW _ж_ж3 ?#" `  R   @`    `HPW _ж_ж3 ?#" `   R   @`%N 2p<  q   N  '  r  2 @  2 s  3 rQW _ж_ж31?#" ` '  KA   2 t  3 rUW _ж_ж31?#" ` ''  KB   2 u  3 rZW _ж_ж31?#" ` '  KC   v   f_ж_ж?"   w   f_ж_ж?"'  , x   f]W _ж_ж3 ?#" `p< D  z2nd ItD   y B # l_ж_ж1?"D q 2   `_ж_ж3 Ԕ?#" ` pv ,$D0  HdW f?"6@ NNN?N W,$0 II e"MII (Minimum Initiation Interval) Constrained by resources and recurrences MII = max {resMII, recMII}& 2F 2 ##  #)##  ## ## #     H  0޽h ?J K M K L N O J P S T V T U W X S Y [ \ ^ \ ] _  ` [ a  s t v  t u w  x s y  ̙33___PPT10+ nD' |W = @B DC' = @BA?%,( < +O%,( < +D' =%(D' =%(D-' =4@BB@BB%()?)?D' =.I7 BBBBB[M 3.33333E-6 -0.01669 L 3.33333E-6 -0.18258 *3>*B ppt_xB ppt_y=@0BBAApBBB5੽<* D' =%(D' =%(DG' =4@BBB B%(D' =1:Bvisible*o3>+B#style.visibility<* %(D' =-6B'blinds(horizontal)*<3<* DM' =%(DN' =%(Dw' =4@BBB B%()))D' =1:Bvisible*o3>+B#style.visibility<*e %(D' =-6B'blinds(horizontal)*<3<*e Dw' =4@BBB B%()))D' =1:Bvisible*o3>+B#style.visibility<* %(D' =-6B'blinds(horizontal)*<3<* D' =%(DG' =4@BBB B%(D' =1:Bvisible*o3>+B#style.visibility<* %(D' =-6B'blinds(horizontal)*<3<* DA' =%(D' =%(D' =A@BBBB0B%(D' =1:Bvisible*o3>+B#style.visibility<* %(+8+0+ 0 +|o 0 ii`d(  Eg(  d~ d s *tX `  X  L    2d# Pw E@    ,d  @   H  *d  H _@    d   d  `ȔX _ж_ж3 ?#" `   R   @` 2 d 3 rhX жж31?#" `   KA  mN    d   ( d  `X _ж_ж3 ?#" `   R   @` 2 d 3 rX жж31?#" `   KB  mN    d  ( H  d  `X _ж_ж3 ?#" `   R   @` 2 d 3 rX жж31?#" `   KC   d  `X _ж_ж3 ?#" `   R   @`0@    +d  k@  H   d  H  d  fX _ж_ж3 ?#" ` H  R   @`2 d C xX жж31?#" `   KD  mN  H  !d  H  "d  `X _ж_ж3 ?#" ` H  R   @` 2 #d 3 rX жж31?#" `   KE   %d  fX _ж_ж3 ?#" ` H h  R   @` 'd  `X _ж_ж3 ?#" ` h  R   @` (d  `X _ж_ж3 ?#" `  R   @` )d  `dX _ж_ж3 ?#" `  R   @` -d H|?"0@NNN?N@ @ + .d H|?"0@NNN?N@ @ K /d B?"0@NNN?N` ` R 1d TGH@I?"0@NNN?N y` L    3d# pyN    4d   N   H  5d   H mN    6d    7d  `b _ж_ж3 ?#" `   R   @` 2 8d 3 r4b жж31?#" `   KA  mN    9d   ( :d  `L b _ж_ж3 ?#" `   R   @` 2 ;d 3 r$b жж31?#" `   KB  mN    d 3 rb жж31?#" `   KC   ?d  `'b _ж_ж3 ?#" `   R   @`@N    @d   mN  H  Ad   H  Bd  `0b _ж_ж3 ?#" ` H  R   @` 2 Cd 3 r|2b жж31?#" `   KD  mN  H  Dd  H  Ed  `+b _ж_ж3 ?#" ` H  R   @` 2 Fd 3 r>b жж31?#" `   KE   Gd  `Hb _ж_ж3 ?#" ` H h  R   @` Hd  `Jb _ж_ж3 ?#" ` h  R   @` Id  `Yb _ж_ж3 ?#" `  R   @` Jd  `Tbb _ж_ж3 ?#" `  R   @` Kd H|?"0@NNN?N@ @ + Ld H|?"0@NNN?N@ @ K Md B?"0@NNN?N` ` R Nd TGH@I?"0@NNN?N y` 8 p  d 7 zN p  d p  [d  flb _ж_ж3 ? #" `   R   @` cd  fub _ж_ж3 ? #" `pp  R   @` dd  f4gb _ж_ж3 ? #" `p  R   @` gd N|?"0@NNN?N  S  hd N|?"0@NNN?N . s T   H  Qd#  p pmN    Rd    Sd  `Ȇb _ж_ж3 ?#" `   R   @` 2 Td 3 rb жж31?#" `   KA  mN    Ud   ( Vd  `Pb _ж_ж3 ?#" `   R   @` 2 Wd 3 rb жж31?#" `   KB  mN    Xd  ( H  Yd  `b _ж_ж3 ?#" `   R   @` 2 Zd 3 rb жж31?#" `   KC  RT   d#   sT  H  ]d#   p ^d  `@b _ж_ж3 ?#" ` H  R   @` 2 _d 3 rdb жж31?#" `   KD  sT  H  `d#   p  ad  `b _ж_ж3 ?#" ` H  R   @` 2 bd 3 rb жж31?#" `   KE   id H? "0@NNN?N  R jd ZGHۀI? "0@NNN?Nm * F $K  d GK  od # lb жж3 ?"$ K  ccycle 6   @` pd # l8b жж3 ?"$,  ccycle 5   @` qd # lb жж3 ?"$u  ccycle 4   @` rd # lb жж3 ?"$X ccycle 3   @` sd # l b жж3 ?"$@ ccycle 2   @` td # l8b жж3 ?"$ ccycle 1   @` F WJ > ud w B vd # l_ж_жD?":J : wd  f@b _ж_ж3 ?"W> WIteration space   8  P dPB yd C xZ_ж_жD? "P zd 3 rpb _ж_ж3 ? " E  LTime   {d  ` _ж_ж3 ?"g z1st ItD   |d@  f_ж_ж1?"ZT }d ZX _ж_ж3 ?"|P z2nd ItD   ~d@  f_ж_ж1?"P d Z _ж_ж3 ?" E  z3rd ItD   d@  f_ж_ж1?" - S 2 d Nf|?"6@`NNN?N_# 2 d Nf|?"6@`NNN?N b  8  @  d0 p T   H  d#   mN    d    d  `  _ж_ж3 ?#" `   R   @` 2 d 3 r жж31?#" `   KA  mN    d   ( d  `$ _ж_ж3 ?#" `   R   @` 2 d 3 r( жж31?#" `   KB  mN    d  ( H  d  `0 _ж_ж3 ?#" `   R   @` 2 d 3 r4 жж31?#" `   KC  sT  H  d#   @@  d  `\+ _ж_ж3 ?#" ` H  R   @` 2 d 3 r@ жж31?#" `   KD  sT  H  d#   @@ d  `|L _ж_ж3 ?#" ` H  R   @` 2 d 3 rM жж31?#" `   KE   d TjJ?"6@`NNN?N  d@  fG1HN jJ?"6@`NNN?N#  7  d NxR f|?"6@ NNN?N  `Kernel(2 d TpW f|?"6@`NNN?N >8Each cluster has its own II Constant Iteration Time (IT)`9 2      r d Nf|?"6@ NNN?Np09 d TLb f?"6@`NNN?N)  ,$0 MIT = max {resMIT, recMIT}l 2#  ## ## #Z2 d T?"6@`NNN?N + ,$@0H d 0޽h ?dd-ddd.dd#d/d dd1d 8d;dKd;d>dLdCdFdMd8dCdNdTdWdgdWdZdhd_dbdidTd_djd{dd|d}d8d~ddTdd ̙33WO___PPT10/+}D'  = @B D' = @BA?%,( < +O%,( < +D' =%(Du' =%(D' =4@BBBB%(D' =1:Bvisible*o3>+B#style.visibility<*d%(D' =A@BBBB0B%(D' =1:Bvisible*o3>+B#style.visibility<*d%(+8+0+d0 + 0 #`(k(  (r ( S n `   X ( H| ̙?"6@`NNN?N7,$D 0 n Profile homogenous architecture!!3 ! X ( Hd- ?"6@`NNN?Nnm( ,$D 0 n Select frequencies and voltages!! ! I ( HD ?"6@`NNN?N P ,$D 0 _Modulo Schedulingf   ( <|?"0@NNN?NA A n,$D 0 ( <|?"0@NNN?N( A A ,$D 0H ( 0޽h ?/@(((((( ̙33 ___PPT10.eP,++?D'  = @B D' = @BA?%,( < +O%,( < +D' =%(D' =%(DD' =A@BBBB0B%(D' =1:Bvisible*o3>+B#style.visibility<*(%(D' =-s6Bwipe(down)*<3<*(D' =%(D' =%(D3' =4@BBBB%(D' =1:Bvisible*o3>+B#style.visibility<*(%(D' =-o6Bwipe(up)*<3<*(D' =%(D@' =A@BBBB0B%(D' =1:Bvisible*o3>+B#style.visibility<*(%(D' =-o6Bwipe(up)*<3<*(D' =%(D' =%(D3' =4@BBBB%(D' =1:Bvisible*o3>+B#style.visibility<*(%(D' =-o6Bwipe(up)*<3<*(D' =%(D@' =A@BBBB0B%(D' =1:Bvisible*o3>+B#style.visibility<*(%(D' =-o6Bwipe(up)*<3<*(++0+(0 ++0+(0 ++0+(0 +s 0  *(   x  c $X `   r  S  `   H  0޽h ? ̙33y___PPT10Y+D='  = @B + 0  t<(  t~ t s * `   ~ t s *p 0   H t 0޽h ? ̙33y___PPT10Y+D='  = @B +$ 0   " (  ~  s * `   ~  s * 0    0 # l0e0eA ( ? ?^  (   0 3 r0e0eA # ? ? g  #    0A ! ? ?  8 ! $D 0B  HD|?"0@NNN?N0 0 ,$@0B  HD|?"0@NNN?N (x@ ,$D 0B   HD|?"0@NNN?N<  ,$@ 0B   HD|?"0@NNN?Nx $ ,$@0B   HD|?"0@NNN?N,$D0B   HD|?"0@NNN?N,$@0B   HD|?"0@NNN?N,$@0B  HD|?"0@NNN?N,$@0  0A & ? ?X 8 & $D0H  0޽h ? ̙33___PPT10+xD'  = @B Da' = @BA?%,( < +O%,( < +D ' =%(D ' =%(DG' =4@BBB B%(D' =1:Bvisible*o3>+B#style.visibility<*%(D' =-6B'blinds(horizontal)*<3<*DG' =4@BBB B%(D' =1:Bvisible*o3>+B#style.visibility<* %(D' =-6B'blinds(horizontal)*<3<* DG' =4@BBB B%(D' =1:Bvisible*o3>+B#style.visibility<* %(D' =-6B'blinds(horizontal)*<3<* DG' =4@BBB B%(D' =1:Bvisible*o3>+B#style.visibility<* %(D' =-6B'blinds(horizontal)*<3<* D' =%(D' =4@BBBB%(D' =1:Bvisible*o3>+B#style.visibility<*%(D ' =%(D ' =%(DG' =4@BBB B%(D' =1:Bvisible*o3>+B#style.visibility<*%(D' =-6B'blinds(horizontal)*<3<*DG' =4@BBB B%(D' =1:Bvisible*o3>+B#style.visibility<* %(D' =-6B'blinds(horizontal)*<3<* DG' =4@BBB B%(D' =1:Bvisible*o3>+B#style.visibility<* %(D' =-6B'blinds(horizontal)*<3<* DG' =4@BBB B%(D' =1:Bvisible*o3>+B#style.visibility<*%(D' =-6B'blinds(horizontal)*<3<*D' =%(D' =4@BBBB%(D' =1:Bvisible*o3>+B#style.visibility<*%(+$Z 0 ((0%7'(  ~  s *8 `     H 3f3f|"`qJ { Compute MIT2 0 ff    T_ж_ж ? ,$@0/  T __"` ,$0 iIT:=MIT$0 2  7  H |"` ,$@0 } Increase IT4 0       T_ж_жAJ A,$@0  @ # l_ж_жG5HtI5 ,$D0  # l _ж_ж|?"`I I,$D0 Select IIs & freqs60  @     C2  # lD _ж_ж|"` @ ,$D 0 eOK?$0 f3    Z_ж_жI ,$D 02  ZX _ж_ж"`q [,$0 fNO&0 2   {    7 #" ,$D0  N f?"6@ NNN?N`  5/4 ns ; 4/3 ns ; 3/2 nsZ @`(  N ?"6@ NNN?N `  dC1  @`'  N@& f?"6@ NNN?N`  c1ns  @`(   N/ ?"6@ NNN?N`  dC0  @`w ! N9 f?"6@ NNN?N`  Supported cycle timesN  @`5 " NB f?"6@ NNN?N` qCluster @`B # Ho ?"0@NNN?N B $ B1 ?"0@NNN?N B % B1 ?"0@NNN?N B & Ho ?"0@NNN?N B ' Ho ?"0@NNN?N B ( B1 ?"0@NNN?N`` B ) Ho ?"0@NNN?N  K * HF f?"6@ NNN?N@ ' ,$0 aIT= 7ns*(2  | + HHL f?"6@ NNN?N@ P9 ' ,$0 II(C0)= 7 /1 = 7 cycles 0 2 ff&c , HQ f?"6@ NNN?N H 0 ,$ 0 yII(C1)= 7 / 1.3333 = 5.250 2 !! a - H,W f?"6@ NNN?N@ H ' ,$ 0 wII(C1)= 7 / 1.25 = 5.6 0 2 !! c . H\ f?"6@ NNN?N G 0 ,$ 0 yII(C1)= 7 / 1.5 = 4.6670 2 !!  / Tf33|?"6@`NNN?N@ 1 ,$@0K 0 Ha f?"6@ NNN?N ,$0 aIT= 8ns*(2  | 1 Hg f?"6@ NNN?N P9 ,$0 II(C0)= 8 / 1= 8 cycles 0 2 ff&` 2 Hk f?"6@ NNN?NpH 0W,$0 vII(C1)= 8 / 1.3333 = 60 2 ff a 3 Hq f?"6@ NNN?N H ,$0 wII(C1)= 8 / 1.25 = 6.4 0 2 !!  4 Tf33|?"6@`NNN?N 1 ,$@0H  0޽h ?O  ̙33C1;1___PPT101+LTZD-'  = @B D-' = @BA?%,( < +O%,( < +D' =%(DW' =%(DT' =A@BBB B0B%(D' =1:Bvisible*o3>+B#style.visibility<*%(D' =-6B'blinds(horizontal)*<3<*DG' =4@BBB B%(D' =1:Bvisible*o3>+B#style.visibility<*%(D' =-6B'blinds(horizontal)*<3<*DT' =A@BBB B0B%(D' =1:Bvisible*o3>+B#style.visibility<*%(D' =-6B'blinds(horizontal)*<3<*D4' =%(D' =%(D' =4@BBBB%(D' =1:Bvisible*o3>+B#style.visibility<*7%(D' =%(Du' =%(D' =4@BBBB%(D' =1:Bvisible*o3>+B#style.visibility<*/%(D' =A@BBBB0B%(D' =1:Bvisible*o3>+B#style.visibility<**%(DA' =%(D' =%(D' =A@BBBB0B%(D' =1:Bvisible*o3>+B#style.visibility<*+%(D#' =%(D' =%(D' =A@BBBB0B%(D' =1:Bvisible*o3>+B#style.visibility<*-%(D' =%(D' =A@BBBB0B%(D' =1:Bvisible*o3>+B#style.visibility<*,%(D' =%( D' =A@BBBB0B%(D' =1:Bvisible*o3>+B#style.visibility<*.%(DM ' =%(D' =%(DG' =4@BBB B%(D' =1:Bvisible*o3>+B#style.visibility<*%(D' =-6B'blinds(horizontal)*<3<*D' =%(DT' =A@BBB B0B%(D' =1:Bvisible*o3>+B#style.visibility<*%(D' =-6B'blinds(horizontal)*<3<*D' =%(D' =A@BBBB0B%(D' =1:Bvisible*o3>+B#style.visibility<*%(D' =4@BBBB%(D' =1:Bvisible*o3>+B#style.visibility<*%(D' =A@BBBB0B%(D' =1:Bvisible*o3>+B#style.visibility<*%(D' =4@BBBB%(D' =1:Bvisible*o3>+B#style.visibility<* %(D' =%(Du' =%(D' =4@BBBB%(D' =1:Bvisible*o3>+B#style.visibility<*4%(D' =A@BBBB0B%(D' =1:Bvisible*o3>+B#style.visibility<*0%(DA' =%(D' =%(D' =A@BBBB0B%(D' =1:Bvisible*o3>+B#style.visibility<*1%(D2' =%(D' =%(D' =A@BBBB0B%(D' =1:Bvisible*o3>+B#style.visibility<*3%(D' =%(D' =A@BBBB0B%(D' =1:Bvisible*o3>+B#style.visibility<*2%(++0+0 ++0+0 ++0+0 ++0+0 ++0+0 ++0+*0 ++0++0 ++0+,0 ++0+-0 ++0+.0 ++0+00 ++0+10 ++0+20 ++0+30 +R= 0 TLp(    Hff|?"6@`NNN?N ,$D0~  s * `     H 3f3f|"`qJ { Compute MIT2 0 ff  |  T_ж_ж ?   T __"`  iIT:=MIT$0 2    H |"`  } Increase IT4 0     0  HX 3f3f|"`,$D 0 vDone40 f f  |  T_ж_жAJ A    f_ж_жG+B#style.visibility<*%(D' =-6B'blinds(horizontal)*<3<*DG' =4@BBB B%(D' =1:Bvisible*o3>+B#style.visibility<*%(D' =-6B'blinds(horizontal)*<3<*DT' =A@BBB B0B%(D' =1:Bvisible*o3>+B#style.visibility<* %(D' =-6B'blinds(horizontal)*<3<* D' =%(DG' =4@BBB B%(D' =1:Bvisible*o3>+B#style.visibility<*%(D' =-6B'blinds(horizontal)*<3<*DT' =A@BBB B0B%(D' =1:Bvisible*o3>+B#style.visibility<* %(D' =-6B'blinds(horizontal)*<3<* DV ' =%(D' =%(DG' =4@BBB B%(D' =1:Bvisible*o3>+B#style.visibility<*%(D' =-6B'blinds(horizontal)*<3<*DT' =A@BBB B0B%(D' =1:Bvisible*o3>+B#style.visibility<*%(D' =-6B'blinds(horizontal)*<3<*D' =%(DT' =A@BBB B0B%(D' =1:Bvisible*o3>+B#style.visibility<*%(D' =-6B'blinds(horizontal)*<3<*DG' =4@BBB B%(D' =1:Bvisible*o3>+B#style.visibility<* %(D' =-6B'blinds(horizontal)*<3<* D' =%(DW' =%(DT' =A@BBB B0B%(D' =1:Bvisible*o3>+B#style.visibility<*%(D' =-6B'blinds(horizontal)*<3<*DG' =4@BBB B%(D' =1:Bvisible*o3>+B#style.visibility<*%(D' =-6B'blinds(horizontal)*<3<*DT' =A@BBB B0B%(D' =1:Bvisible*o3>+B#style.visibility<*%(D' =-6B'blinds(horizontal)*<3<*D' =%(D' =%(D-' =4@BBBB%(D' =1:Bvisible*o3>+B#style.visibility<*%(D' =-i6B wedge*<3<*++0+0 ++0+ 0 ++0+ 0 ++0+0 ++0+0 ++0+0 ++0+0 + 0 l6(  l~ l s *0غ `   x l c $T `P   H l 0޽h ? ̙33y___PPT10Y+D='  = @B +u4 0   #3P(  ~  s *X `   x  c $0 0`    ' T gֳgֳ ? p$0<4___PPT9 92-cycle latency instructions 4 clusters, 1 FU per cluster4pd: :  ( T gֳgֳ ? Hi ,$0 [Homogeneous Recurrence: 6 cycles II= 6 cycles (all clusters!) lots of unused slotsH  ;  9 \ cl ` 2`,$D0R  ZGHI?"0@NNN?N i T CR $# ` 2  C x< _ж_ж31?#" `CQ KA  2  C x̱ _ж_ж31?#" `C"Q0 KB  2  C x _ж_ж31?#" `CQ KC     # l_ж_ж?""   # l_ж_ж?"0b ! TGv/HIM?"0@NNN?NQR9R #  `GKHIK?"0@NNN?NG  @   - 2  C x0 _ж_ж31?#" `   KH  2  C xp _ж_ж31?#" `p ~  KI  2  C x8 _ж_ж31?#" ` KJ    H?"0@NNN?Ni ip   H?"0@NNN?Ni~ i 2 ) 3 r _ж_ж31?#" ` KK   * B?"0@NNN?Nii@   . 2   C xX _ж_ж31?#" `   KD  2   C xؿ _ж_ж31?#" `p ~  KE  2   C xL _ж_ж31?#" ` KF    # l_ж_ж?"G Gp   # l_ж_ж?"G~ G 2 + 3 r _ж_ж31?#" ` KG   , B?"0@NNN?NGGh / T gֳgֳ ? i,$0 NHeterogeneous 1 fast cluster, cycle time= 1ns 3 slow clusters, cycle time= 2ns2  !A O  0 H f?"6@ NNN?N H@,$ 0 0IT= 6ns II(fast cluster)= 6 II(slow clusters)= 311 Z 1 Tf|?"6@`NNN?N JA,$@ 0 3 ZG0*HKf|?"6@`NNN?N@  ,$D0H  0޽h ?`       ! #)* +, ̙33:2___PPT10.Ta ^+*7D'  = @B D' = @BA?%,( < +O%,( < +D' =%(D' =%(DG' =4@BBB B%(D' =1:Bvisible*o3>+B#style.visibility<*2%(D' =-6B'blinds(horizontal)*<3<*2D' =%(DT' =A@BBB B0B%(D' =1:Bvisible*o3>+B#style.visibility<*'%(D' =-6B'blinds(horizontal)*<3<*'D' =%(Du' =%(D' =A@BBBB0B%(D' =1:Bvisible*o3>+B#style.visibility<*(%(D' =4@BBBB%(D' =1:Bvisible*o3>+B#style.visibility<*3%(DA' =%(D' =%(D' =A@BBBB0B%(D' =1:Bvisible*o3>+B#style.visibility<*/%(D'' =%(D' =%(D1' =4@BBBB%(D' =1:Bvisible*o3>+B#style.visibility<*1%(D' =-m6Bbox(in)*<3<*1D>' =A@BBBB0B%(D' =1:Bvisible*o3>+B#style.visibility<*0%(D' =-m6Bbox(in)*<3<*0++0+'0 ++0+(0 ++0+/0 ++0+00 + 0 @ 6(   ~   s *,} `  }  x   c $ }   }  H   0޽h ? ̙33y___PPT10Y+D='  = @B + 0 6(  ~  s *@T `   x  c $U `P   H  0޽h ? ̙33y___PPT10Y+D='  = @B + 0 ^ V   (  ~  s *r `    0 HA E ?0` E  #  Hs f?"6@ NNN?N mED2:(2  =   Hy f?"6@ NNN?NX,$0 S35% (2 =   H<~ f?"6@ NNN?N ,$0 S30% (2 2   H33?"6@`NNN?N ,$@02  H33?"6@`NNN?N ,$D0=  HĂ f?"6@ NNN?N,$0 S17% (2 2  H33?"6@`NNN?N`,$@02  Bf|?"6@`NNN?NQ,$D0H  0޽h ? ̙33 ___PPT10._ƒ+AWD'  = @B D ' = @BA?%,( < +O%,( < +D' =%(Du' =%(D' =4@BBBB%(D' =1:Bvisible*o3>+B#style.visibility<*%(D' =A@BBBB0B%(D' =1:Bvisible*o3>+B#style.visibility<*%(D' =%(D' =%(D' =A@BBBB0B%(D' =1:Bvisible*o3>+B#style.visibility<* %(D' =4@BBBB%(D' =1:Bvisible*o3>+B#style.visibility<* %(D' =A@BBBB0B%(D' =1:Bvisible*o3>+B#style.visibility<* %(D' =4@BBBB%(D' =1:Bvisible*o3>+B#style.visibility<*%(D4' =%(D' =%(D' =4@BBBB%(D' =1:Bvisible*o3>+B#style.visibility<*%(++0+ 0 ++0+ 0 ++0+0 +  0 7/4p(  ~  s *X `   x  c $0 `   ]8 ``  3( R  ZGyBH&IyB?"0@NNN?N"2   C xD _ж_ж31?#" `y`n KA  R   `G${HTI${?"0@NNN?Ny BT B"P  /# " 2  C x _ж_ж31?#" `B"P0  KH  2  C x _ж_ж31?#" `B P  KI    H?"0@NNN?N0  <T ` n  .# ` n 2  C x _ж_ж31?#" `` n.  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H8 f?"6@ NNN?N  mED2:(2  # " H f?"6@ NNN?N)  mED2:(2   # Hx f?"6@ NNN?N  Q1 bus(2 # $ H f?"6@ NNN?N@` m2 buses(2&H  0޽h ? ̙33___PPT10i._ƒ+D='  = @B +4 0   p##,(  ,~ , s *} `  }  x , c $$} 0` }   , Ta} gֳgֳ ? r$0>6___PPT9 92-cycle latency instructions 4 clusters, 1 FU per cluster4pd: :  , TL} gֳgֳ ? Hi ,$0 [Homogeneous Recurrence: 6 cycles II= 6 cycles (all clusters!) lots of unused slotsH  ;  9 \ 'z ` , `,$D0R , TGHI?"0@NNN?N i T CR ,# `  2  , 3 r+B#style.visibility<*,%(D' =-6B'blinds(horizontal)*<3<*,D' =%(DT' =A@BBB B0B%(D' =1:Bvisible*o3>+B#style.visibility<*,%(D' =-6B'blinds(horizontal)*<3<*,D' =%(Du' =%(D' =A@BBBB0B%(D' =1:Bvisible*o3>+B#style.visibility<*,%(D' =4@BBBB%(D' =1:Bvisible*o3>+B#style.visibility<*#,%(DA' =%(D' =%(D' =A@BBBB0B%(D' =1:Bvisible*o3>+B#style.visibility<* ,%(D'' =%(D' =%(D1' =4@BBBB%(D' =1:Bvisible*o3>+B#style.visibility<*",%(D' =-m6Bbox(in)*<3<*",D>' =A@BBBB0B%(D' =1:Bvisible*o3>+B#style.visibility<*!,%(D' =-m6Bbox(in)*<3<*!,++0+,0 ++0+,0 ++0+ ,0 ++0+!,0 + 0 p | *(  | x | c $ `   r | S ܖ `   H | 0޽h ? ̙33___PPT10i.Ta ^+D='  = @B +00 P (   X  C <\     S   6b     H  0bf ? ̙330 ( (  ( X ( C <\     ( S l  6b      H ( 0bf ? ̙33Ax0 p (   d  c $<\      s *  6b    {In this work we focus on VLIW architecutres Require less power Because they execute in order So the compiler plays a critical role In particular we study spill code generation When register requirements are too high we can introduce store a value to memory to free up a register Dir de paraula que ho farem per loops modulo scheduled q suporten molta pressio sobre registres pq se solapen instruccionsj,W.h{,W.h{D                            H  0bf ? ̙33r0 2*  (   d  c $<\      s *,  6b    *To schedule the loops we use MS& & which is an effective software pipelining technique that overlaps the execution of different iterations of a loop A new iteration can be started before the previous one has finished Hence, it increases parallelism But at the expense of putting additional pressure on resources In particular, on registers After a certain number of cycles we reach a stable state: kernel We iterate the kernel every II cycles The instructions launched in each kernel iteration belong to different original iterations<  H  0bf ? ̙33*^0   :(   X  C <\      S P  6b    <  H  0bf ? ̙3380___PPT10.hk@8<0 @ 8(  8X 8 C <\     8 S    6b      H 8 0bf ? ̙3380___PPT10.Pp /0  d*(  d^ d S <\     d c $  6b      H d 0bf ? ̙33 0  ~  (  d  c $<\    r   s *X&  6b   ___PPT9 D L So let s go... Development of technology allows us to Put more logic in a chip Use faster clocks However, this development generates new challenges. May be the 3 main issues that the researchers have to face up are& the delay of the wires relative to the delay of the gates One promising technique to deal with these difficulties is the design of the microprocessor with clusters. In this way, the system is divided in computational units that can work almost independently. Each one of these units is called cluster and is typically composed of some functional units and a local register file. The rest of resources are centralized. Then, some inter-cluster network is required to communicate values among clusters. !!!! no dir busos pq hi ha altres maneres d interconnexio!!!! In fact, clustering is already a common trend in commercial VLIW processors. VLIW processors are very popular in the DSP and the embedded domain&',w;" l`1ND ' , w ;   l ` 1   N$$ D((    H  0bf ? ̙330 (  ^  S <\    |  c $ .  6b   ___PPT9d\ ~xHere we can see a picture of a clustered architecture N clusters an interconnection network (we have assumed buses) centralized data cache The figure on the right is a cluster It s own register file Can access the bus Functional units and memory ports Memory ports access the centralized cache Instruction cache6X" &" " "" *" 6X& "* = H  0bf ? ̙33j0 *"0(  d  c $<\      s *F  6b   xp___PPT9RJ $BThen, for statically scheduled processors (such as VLIW) performance relies very much on the compiler For such architectures, it is very important to make a good instruction scheduling. This is a complex task because: resource constraints dependences among instructions Besides, if we are targeting a clustered architecture, there is an additional problem communications & In this work we focus on instruction scheduling for loops. in particular, we use MS MS is a technique that overlaps the execution of different iterations of loop Very effective for multimedia and numeric code Therefore, MS puts additional pressure on resources In particular, on the register buses6" VTO6VT O  H  0bf ? ̙33 0  ~ P  (   d   c $<\    r    s *\  6b   ___PPT9 D L So let s go... Development of technology allows us to Put more logic in a chip Use faster clocks However, this development generates new challenges. May be the 3 main issues that the researchers have to face up are& the delay of the wires relative to the delay of the gates One promising technique to deal with these difficulties is the design of the microprocessor with clusters. In this way, the system is divided in computational units that can work almost independently. Each one of these units is called cluster and is typically composed of some functional units and a local register file. The rest of resources are centralized. Then, some inter-cluster network is required to communicate values among clusters. !!!! no dir busos pq hi ha altres maneres d interconnexio!!!! In fact, clustering is already a common trend in commercial VLIW processors. VLIW processors are very popular in the DSP and the embedded domain&',w;" l`1ND ' , w ;   l ` 1   N$$ D((    H   0bf ? ̙33 0  ~ p( (  (d ( c $<\    r  ( s *h  6b   ___PPT9 D L So let s go... Development of technology allows us to Put more logic in a chip Use faster clocks However, this development generates new challenges. May be the 3 main issues that the researchers have to face up are& the delay of the wires relative to the delay of the gates One promising technique to deal with these difficulties is the design of the microprocessor with clusters. In this way, the system is divided in computational units that can work almost independently. Each one of these units is called cluster and is typically composed of some functional units and a local register file. The rest of resources are centralized. Then, some inter-cluster network is required to communicate values among clusters. !!!! no dir busos pq hi ha altres maneres d interconnexio!!!! In fact, clustering is already a common trend in commercial VLIW processors. VLIW processors are very popular in the DSP and the embedded domain&',w;" l`1ND ' , w ;   l ` 1   N$$ D((    H ( 0bf ? ̙33 0  ~ 4 (  4d 4 c $<\    r  4 s *  6b   ___PPT9 D L So let s go... Development of technology allows us to Put more logic in a chip Use faster clocks However, this development generates new challenges. May be the 3 main issues that the researchers have to face up are& the delay of the wires relative to the delay of the gates One promising technique to deal with these difficulties is the design of the microprocessor with clusters. In this way, the system is divided in computational units that can work almost independently. Each one of these units is called cluster and is typically composed of some functional units and a local register file. The rest of resources are centralized. Then, some inter-cluster network is required to communicate values among clusters. !!!! no dir busos pq hi ha altres maneres d interconnexio!!!! In fact, clustering is already a common trend in commercial VLIW processors. VLIW processors are very popular in the DSP and the embedded domain&',w;" l`1ND ' , w ;   l ` 1   N$$ D((    H 4 0bf ? ̙330 H(  H^ H S <\   | H c $l  6b  ___PPT9d\ ~xHere we can see a picture of a clustered architecture N clusters an interconnection network (we have assumed buses) centralized data cache The figure on the right is a cluster It s own register file Can access the bus Functional units and memory ports Memory ports access the centralized cache Instruction cache6X" &" " "" *" 6X& "* = H H 0bf ? ̙33 0  ~ 0X (  Xd X c $<\   r  X s *X%  6b  ___PPT9 D L So let s go... Development of technology allows us to Put more logic in a chip Use faster clocks However, this development generates new challenges. May be the 3 main issues that the researchers have to face up are& the delay of the wires relative to the delay of the gates One promising technique to deal with these difficulties is the design of the microprocessor with clusters. In this way, the system is divided in computational units that can work almost independently. Each one of these units is called cluster and is typically composed of some functional units and a local register file. The rest of resources are centralized. Then, some inter-cluster network is required to communicate values among clusters. !!!! no dir busos pq hi ha altres maneres d interconnexio!!!! In fact, clustering is already a common trend in commercial VLIW processors. VLIW processors are very popular in the DSP and the embedded domain&',w;" l`1ND ' , w ;   l ` 1   N$$ D((    H X 0bf ? ̙33j0 *"ph(  hd h c $<\    h s *DR  6b  xp___PPT9RJ $BThen, for statically scheduled processors (such as VLIW) performance relies very much on the compiler For such architectures, it is very important to make a good instruction scheduling. This is a complex task because: resource constraints dependences among instructions Besides, if we are targeting a clustered architecture, there is an additional problem communications & In this work we focus on instruction scheduling for loops. in particular, we use MS MS is a technique that overlaps the execution of different iterations of loop Very effective for multimedia and numeric code Therefore, MS puts additional pressure on resources In particular, on the register buses6" VTO6VT O  H h 0bf ? ̙3360 pF(  p^ p S <\    p c $e  6b   <  H p 0bf ? ̙3380___PPT10.hk@8<0 xpx(  x^ x S <\   j x c $  6b   The IT has to be big enough to accommodate the Instructions The register requirements The communications Of the profiled homogeneous</:/:y   H x 0bf ? ̙3380___PPT10.hk@8< 0  ~  (  d  c $<\   r   s *`  6b  ___PPT9 D L So let s go... Development of technology allows us to Put more logic in a chip Use faster clocks However, this development generates new challenges. May be the 3 main issues that the researchers have to face up are& the delay of the wires relative to the delay of the gates One promising technique to deal with these difficulties is the design of the microprocessor with clusters. In this way, the system is divided in computational units that can work almost independently. Each one of these units is called cluster and is typically composed of some functional units and a local register file. The rest of resources are centralized. Then, some inter-cluster network is required to communicate values among clusters. !!!! no dir busos pq hi ha altres maneres d interconnexio!!!! In fact, clustering is already a common trend in commercial VLIW processors. VLIW processors are very popular in the DSP and the embedded domain&',w;" l`1ND ' , w ;   l ` 1   N$$ D((    H  0bf ? ̙3360 @F(  ^  S <\     c $س  6b   <  H  0bf ? ̙3380___PPT10.hk@8<0 *(  ^  S <\     c $  6b     H  0bf ? ̙3380___PPT10.Pp~,0 *(  ^  S <\     c $  6b     H  0bf ? ̙3380___PPT10.Pp /0 *(  ^  S <\     c $  6b     H  0bf ? ̙3380___PPT10.Pp /0 *(  ^  S <\     c $  6b     H  0bf ? ̙3380___PPT10.Pp /60 F(  ^  S <\     c $h  6b   <  H  0bf ? ̙3380___PPT10.hk@8<0 0*(  ^  S <\     c $1  6b     H  0bf ? ̙3380___PPT10.Pp~,60 F(  ^  S <\     c $D  6b   <  H  0bf ? ̙3380___PPT10.hk@8<0 ( (  ^  S <\     c $  6b   jUse the profiled homogeneous architecture as baseline Compute relative power with respect to this baselinekk k H  0bf ? ̙3380___PPT10.hk@8< 0  ~  (  d  c $<\   r   s *'!  6b  ___PPT9 D L So let s go... Development of technology allows us to Put more logic in a chip Use faster clocks However, this development generates new challenges. May be the 3 main issues that the researchers have to face up are& the delay of the wires relative to the delay of the gates One promising technique to deal with these difficulties is the design of the microprocessor with clusters. In this way, the system is divided in computational units that can work almost independently. Each one of these units is called cluster and is typically composed of some functional units and a local register file. The rest of resources are centralized. Then, some inter-cluster network is required to communicate values among clusters. !!!! no dir busos pq hi ha altres maneres d interconnexio!!!! In fact, clustering is already a common trend in commercial VLIW processors. VLIW processors are very popular in the DSP and the embedded domain&',w;" l`1ND ' , w ;   l ` 1   N$$ D((    H  0bf ? ̙33 0  ~  (  d  c $<\   ! r   s *%!  6b  !