CGO 2007 Advance Program

Conference at a Glance

Sunday, 11 March 2007
List of Workshops and Tutorials Note that Daylight Savings Time starts in the US on that day.
7:30 Continental breakfast
8:00 Morning session starts
10:00 Morning break
12:00-13:30 Lunch (included for all tutorial/workshop attendees)
1:30 Afternoon session starts
3:30 Break
6:00 Afternoon session ends
Monday, 12 March 2007
7:30 Continental breakfast Sponsored by AMD
8:00-8:15 Welcome
8:15-9:15 Session 1 Transactions
9:45-11:15 Session 2 Run-Time Optimization and JIT
11:45-12:45 Lunch
1:15-2:45 Session 3 Optimization I
3:15-5:15 Session 4 Guiding Optimizations
5:30-6:00 Reception
6:00-7:00 Panel Are new languages necessary for multicore?
7:00-9:00 Dinner on your own
9:00 Business Meeting
Tuesday, 13 March 2007
7:45 Continental breakfast Sponsored by Intel
8:30-9:30 Keynote Ian Buck, NVIDIA
10:00-11:30 Session 5 Profiling and Instrumentation
11:30-13:30 Lunch on your own
1:30-3:00 Session 6 Special Issues
3:30-5:00 Session 7 Optimization II
5:30-9:00 Evening at Google
Wednesday, 14 March 2007
7:30 Continental breakfast
8:00-9:30 Session 8 Memory Optimization
10:00-11:30 Session 9 Novel Architectures
11:30-12:00 CGO Closing Closing and Awards
12:30-13:00 Lunch
13:00-14:00 Keynote Jesse Fang, Intel

Detailed Program

Sunday, 11 March 2007
Workshops and Tutorials

Click here for a schedule.
Monday, 12 March 2007
Session 1: Transactions
Session Chair: Christos Kozyrakis, Stanford University
Understanding Tradeoffs in Software Transactional Memory Dave Dice (Sun Microsystems) and Nir Shavit (Sun Microsystems and Tel-Aviv University). Slides:
Code Generation and Optimization for Transactional Memory Constructs in an Unmanaged Language Cheng Wang (Intel Corporation), Wei-Yu Chen (University of California, Berkeley), Youfeng Wu, Bratin Saha, and Ali-Reza Adl-Tabatabai (Intel Corporation) Slides: pdf, ppt.
Session 2: Run-Time Optimization and JIT
Session Chair: Cliff Click, Azul Systems
Run-Time Support for Optimizations Based on Escape Analysis Thomas Kotzmann and Hanspeter Mössenböck (Johannes Kepler University Linz) Slides:
Evaluating Indirect Branch Handling Mechanisms in Software Dynamic Translation Systems Jason D. Hiser, Daniel Williams, Wei Hu, Jack W. Davidson (University of Virginia), Jason Mars, and Bruce R. Childers (University of Pittsburgh) Slides: ppt.
Persistent Code Caching: Exploiting Code Reuse across Executions and Applications Vijay Janapa Reddi (Harvard University), Dan Connors (University of Colorado at Boulder), Robert Cohn (Intel), and Michael D. Smith (Harvard University) Slides: ppt.
Session 3: Optimization I
Session Chair: Teresa Johnson, Hewlett Packard
Virtual Cluster Scheduling through the Scheduling Graph Josep M. Codina (UPC and Intel Barcelona Research Center), Jesús Sánchez (Intel Barcelona Research Center, UPC), and Antonio González (UPC and Intel Barcelona Research Center) Slides:
On the Complexity of Register Coalescing Florent Bouchez, Alain Darte, and Fabrice Rastello (LIP UMR CNRS-ENS Lyon-UCB Lyon-Inria) Slides: pdf.
A Dimension Abstraction Approach to Vectorization in Matlab Neil Birkbeck, Jonathan Lévesque, and José Nelson Amaral (University of Alberta) Slides: ppt.
Session 4: Guiding Optimizations
Session Chair: Andy Ayers, Microsoft
Microarchitecture Sensitive Empirical Models for Compiler Optimizations Kapil Vaswani, Matthew J. Thazhuthaveetil, Y. N. Srikant (Indian Institute of Science, Bangalore), and P. J. Joseph (Freescale, India)
Iterative Optimization in the Polyhedral Model: Part I, One-Dimensional Time Louis-Noël Pouchet, Cédric Bastoul, Albert Cohen, and Nicolas Vasilach (INRIA FUTURS and Paris-Sud University) Slides:
Evaluating Heuristic Optimization Phase Order Search Algorithms Prasad A. Kulkarni, David B. Whalley, Gary S. Tyson (Florida State University), and Jack W. Davidson (University of Virginia) Slides: pdf.
Loop Optimization Using Hierarchical Compilation and Kernel Decomposition Barthou Denis (Université de Versailles Saint-Quentin), Sebastien Donadio (Université de Versailles Saint-Quentin and BULL SA), Patrick Carribault (BULL SA, LRC ITACA, CEA/DAM, Université de Versailles Saint-Quentin), Alexandre Duchateau (LRC ITACA, CEA/DAM, Université de Versailles Saint-Quentin), and William Jalby (Université de Versailles and LRC ITACA, CEA/DAM)> Slides: pdf.

Panel discussion
Session Chairs: Michael Paleczny, Sun and Carol Eidt, Microsoft
Are new languages necessary for multicore?

CGO-5 is inviting industry practitioners to join the conference attendees for a complimentary reception and panel discussion on Monday evening, March 12. We have invited the following panelists to share their perspectives: David August (Princeton), Preston Briggs (AMD), David Callahan (Microsoft), David Chase (Sun), Edward Lee (Berkeley). Please join us to meet and interact with academic and industry experts interested in topics ranging from compiler optimizations, run-time profiling, and memory optimizations to transactional memory and novel architectures. Although there is no charge for this event, advance registration for those not already registered for CGO is required due to limited seating. Bios and position statements.

Slides: David August, David Callahan, David Chase, Edward Lee.

Business Meeting

Tuesday, 13 March 2007
Keynote: Ian Buck, NVIDIA
Session Chair: Christos Kozyrakis, Stanford University
GPU Computing: Programming a Massively Parallel Processor Ian Buck, NVIDIA, GPU-Compute Software Manager (
abstract, slides in pdf)
Session 5: Profiling and Instrumentation
Session Chair: Michael Paleczny, Sun
Rapidly Selecting Good Compiler Optimizations Using Performance Counters John Cavazos (University of Edinburgh), Grigori Fursin (INRIA Futurs and Paris-Sud University), Felix Agakov, Edwin Bonilla, Michael F. P. O'Boyle (University of Edinburgh), and Olivier Temam (INRIA Futurs and Paris-Sud University) Slides:
Shadow Profiling: Hiding Instrumentation Costs with Parallelism Tipp Moseley, Alex Shye, Vijay Janapa Reddi, Dirk Grunwald (University of Colorado at Boulder), and Ramesh Peri (Intel Corporation) Slides: ppt.
SuperPin: Parallelizing Dynamic Instrumentation for Real-Time Performance Steven Wallace (Intel Corporation) and Kim Hazelwood (University of Virginia) Slides: pdf.
Session 6: Special Issues
Session Chair: Jens Knoop, TU Vienna, Austria
Compilation Techniques for Real-Time Java Programs Mike Fulton and Mark Stoodley (IBM Canada) Slides:
Compiler-Directed Variable Latency Aware SPM Management to Cope with Timing Problems O. Ozturk, G. Chen, M. Kandemir (Pennsylvania State University), and M. Karakoy (Imperial College) Slides: ppt.
Compiler-Managed Software-Based Redundant Multi-threading for Transient Fault Detection Cheng Wang, Ho-seop Kim, Youfeng Wu, and Victor Ying (Intel Corporation) Slides: ppt.
Session 7: Optimization II
Session Chair: Nacho Navarro, UPC, Spain
Graph-Based Procedural Abstraction A. Dreweke, M. Wörlein (University of Erlangen-Nuremberg), I. Fischer (University of Konstanz), D. Schell (University of Erlangen-Nuremberg), T. Meinl (University of Konstanz), and M. Philippsen (University of Erlangen-Nuremberg) Slides:
Structure Layout Optimization for Multithreaded Programs Easwaran Raman (Princeton University), Robert Hundt, and Sandya S. Mannarswamy (Hewlett-Packard) Slides: ppt, pptx.
Code Compaction of an Operating System Kernel Haifeng He, John Trimble, Somu Perianayagam, Saumya Debray, and Gregory Andrews (University of Arizona) Slides: ppt.
Evening at Google

Here's the tentative agenda:
5:30pmGoogle will pick up the conference attendees and organizers at the Hotel Valencia Santana Row
7-8Google presentation/CGO representative speaks
8-9Networking and close
9:00-9:30shuttle buses back to hotel

There will be directional signs up around campus for the folks who drive on their own. This map shows the Google campus with parking spots outlined in the legend. The event will be held in building 43 so all attendees should go to the lobby of that building for registration.

Wednesday, 14 March 2007
Session 8: Memory Optimizations
Session Chair: Olof Lindholm, BEA
Ubiquitous Memory Introspection Qin Zhao (Singapore-MIT Alliance and National University of Singapore), Rodric Rabbah (IBM T.J. Watson Research Center), Saman Amarasinghe, Larry Rudolph (Singapore-MIT Alliance, Massachusetts Institute of Technology), and Weng-Fai Wong (Singapore-MIT Alliance and National University of Singapore) Slides:
Pipelined Execution of Critical Sections Using Software-Controlled Caching in Network Processors Jinquan Dai, Long Li, and Bo Huang (Intel China Software Center) Slides: ppt.
Isla Vista Heap Sizing: Using Feedback to Avoid Paging Chris Grzegorczyk, Sunil Soman, Chandra Krintz, and Rich Wolski (University of California at Santa Barbara) Slides: ppt.
Session 9: Novel Architectures
Session Chair: Carol Eidt, Microsoft
Exploiting Narrow Accelerators with Data-Centric Subgraph Mapping Amir Hormati, Nathan Clark, and Scott Mahlke (University of Michigan-Ann Arbor) Slides:
Heterogeneous Clustered VLIW Microarchitectures Àlex Aletà (UPC), Josep M. Codina, Antonio González (UPC and Intel Barcelona Research Center), and David Kaeli (Northeastern University) Slides: pdf, pps.
Profile-Assisted Compiler Support for Dynamic Predication in Diverge-Merge Processors Hyesoon Kim, José A. Joao (University of Texas at Austin), Onur Mutlu (Microsoft Research), and Yale N. Patt (University of Texas at Austin) Slides: pdf.
Keynote: Jesse Fang, Intel
Session Chair: Ali-Reza Adl-Tabatabai, Intel
Parallel Programming Environment: A Key to Translating Tera-Scale Platforms into a Big Success Jesse Fang, Intel, Director of Programming Systems Lab (